1. Field of the Invention
The present invention relates to a memory control device.
2. Description of the Related Art
In recent years, cellular telephones, printers, scanners and other such apparatuses are provided with a custom IC called an ASIC (Application Specific Integrated Circuit), to achieve compactness, high-performance, and high-quality. The ASIC is an IC composed by combining various basic circuits to specialize for a specific usage purpose, and is convenient because a main portion of a control circuit in the apparatus can be realized with one chip. In accordance with the conventional printer apparatus, the ASIC is used to control transmission and reception of a data signal between a CPU governing controls and a memory device performing transmission and reception of data to and from the CPU.
On the other hand, in a memory device equipped with a DRAM (Dynamic Random Access Memory) operating in synchronization with the clock, for example, an SDRAM (Synchronous DRAM) or a DDR SDRAM (Double Data Rate SDRAM), the data transmission and reception based on the synchronization clock is performed. In order to control the memory device, when a data signal is outputted to a data bus connecting the ASIC and the memory device, the following signals are used for the control: a data enable signal (hereinafter, referred to as a “data_enable signal”) and a data out signal (hereinafter, referred to as a “data_out signal”). The data_enable signal is for controlling whether to output data to or to input data from the memory device, and is in either a high level (hereinafter, referred to as “H”) or a low level (hereinafter, referred to as “L”) state. The data_out signal is used as the data signal when the data_enable signal indicates that data is to be output to the memory device. The data_out signal is also in either an H or L state. Then, in the ASIC and the memory device, data signal processing such as transmission and reception and storage are performed at a timing of a rise of the synchronization clock.
Incidentally, the ASIC includes an internal buffer for performing 3-state output, wherein the data_out signal is outputted to the data bus only when the state of the data_enable signal is H.